摘要
给出了一种适用于分时采样结构A/D转换器的等间距8相时钟发生电路。介绍了延迟锁相环(DLL)的结构,给出了每一模块的具体模型并加以分析。在0.18μm标准CMOS工艺和1.8V电源电压下,对电路进行了模拟仿真。仿真结果显示,在1.25GHz的参考输入频率下,DLL输入每相延迟100ps,锁定时间6.48ns,总功耗为79mW。
An 8-phase clock generator for time-interleaved ADC was presented.The architecture of delay locked loop（DLL） was analyzed,and design of each block of the DLL circuit was described in detail.Based on 0.18 μm CMOS process,the circuit was simulated at 1.8 V supply voltage,Simulation results showed that,for 1.25 GHz reference input frequency,the DLL had a delay time of 100 ps/phase and a locking time of 6.48 ns with a total power of 79 mW.
出处
《微电子学》
CAS
CSCD
北大核心
2013年第1期19-22,共4页
Microelectronics
关键词
延迟锁相环
压控延迟线
鉴相器
电荷泵
Delay locked loop
Voltage controlled delay line
Phase detector
Charge pump
