适用于编译器的高速SRAM阵列及外围设计

Design of High-Speed SRAM Array and Peripheral Circuits for Compiler

SRAM编译器一般需要配置具有各种字宽、各种容量的SRAM。针对这种需求,SRAM阵列和外围电路需要设计成具有可配置性、可复用性的结构。使用0.525μm2的6管存储单元,采用阵列划分、两级译码和具有本地时序的灵敏放大器,实现了适用于编译器的高速SRAM设计。基于SMIC 65nm CMOS工艺,对512kb的SRAM进行流片验证。测试结果表明,该SRAM在1.2V工作电压下可实现1.06ns的高速访问时间。

SRAM compiler needs a variety of SRAMs with different sizes and word widths for configuration.To meet this demand,SRAM array and peripheral circuits should be designed as configurable and reusable.Based on 0.525 μm2 6T SRAM cell,a high-speed SRAM was designed for compiler using array partitioning,two-stage decoder and sense amplifier with local timing control.A 512 kb SRAM was fabricated based on SMIC＇s 65 nm CMOS process.Test results showed that the SRAM had an access time of 1.06 ns at 1.2 V operating voltage.