降低数字集成电路测试功耗的向量排序方法

A Novel Technique for Reducing Power Consumption in IC Test by Vector Ordering

研究了数字集成电路测试过程中的功耗问题,提出一种新的测试向量重排序方法,有效地减小了测试过程中电路状态的翻转次数。该方法根据电路结构和测试集的特征计算输入的影响度系数,定义加权海明距离,在不影响故障覆盖率的前提下,有效地降低了测试功耗。实验结果显示,经过该方法重排序后的测试集在测试过程中功耗平均降低48.07%,明显优于海明距离法。

High power dissipation of digital IC＇s in test mode was studied,and a novel technique based on reordering of test vectors was proposed,in which both circuit structure and test set were taken into consideration.In this technique,a weight was used to quantify the relationship between the switching of each input and the internal switching activity,and test set was reordered based on these weights.Experimental results showed that,by using this method,the power consumption was reduced by 48.07% in average during external test application,which was remarkably better than Hamming distance method.