期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

基于概率转移矩阵的时序电路可靠度估计方法 被引量：12

Reliability Estimation of Sequential Circuit Based on Probabilistic Transfer Matrices
下载PDF
导出
摘要 传统的概率转移矩阵(Probabilistic Transfer Matrix,PTM)方法是一种能够比较精确地估计软差错对门级电路可靠度影响的方法,但现有的方法只适用于组合逻辑电路的可靠度估计.本文提出基于PTM的时序电路可靠度估计方法(reliability estimation of Sequential circuits based on PTM,S-PTM),先把待评估时序电路划分为输出逻辑模块和次态逻辑模块,然后用本文提出的时序电路PTM计算模型得到电路的PTM,最后根据输入信号的概率分布计算出时序电路的可靠度.用ISCAS 89基准电路为对象进行实验和验证,实验表明所提方法是准确和合理的. Traditional method based on probabilistic transfer matrices（PTM） for estimate the effects of soft errors on gate level circuit reliability can only be used for combinational circuits.In this paper,a method for reliability estimation of sequential circuit based on PTM（S-PTM） is proposed.A sequential circuitis divided into an output logic module and a next state logic module,then the PTM of the sequential circuit is calculated by deduction employing the proposed PTM calculation model for sequential circuits in the paper.Considering probability distribution of the circuit inputs,the reliability of overall circuit is estimated.Experimental results on ISCAS 89 benchmark circuits show that our method is efficient.
作者 欧阳城添 江建慧
机构地区 同济大学软件学院 江西理工大学信息工程学院
出处 《电子学报》 EI CAS CSCD 北大核心 2013年第1期171-177,共7页 Acta Electronica Sinica
基金 国家自然科学基金(No.60903033)
关键词 软差错 时序电路 可靠度估计 概率转移矩阵 半张量积 soft error sequential circuit reliability estimation probabilistic transfer matrix semi-tensor product
分类号 TP302.8 [自动化与计算机技术—计算机系统结构]
  • 相关文献

参考文献18

  • 1S S Mukherjee,J Emer,S K Reinhhardt. The soft error problem:An architectural perspective[A].Washing,DC,USA:IEEE Computer Society,2005.243-247.
  • 2J F Ziegler,H W Curtis,H P Muhlfeld. IBM experiments in soft fails in computer electronics (1978-1994)[J].IBM Journal of Research and Development,1996,(01):3-18.doi:10.1147/rd.401.0003.
  • 3T C May,M H Woods. Alpha-particle-induced soft errors in dynamic memories[J].IEEE Transactions on Electron Devices,1979,(01):2-9.
  • 4N Miskov-Zivanov,D Marculescu. Soft error rate analysis for sequential circuits[A].Nice,France:IEEE Computer Society,2007.1-6.
  • 5N Miskov-Zivanov,D Marculescu. Modeling and optinization for soft-Error reliability of sequential circuits[J].IEEE Trinsactions on Computer-Aided Design of Integrated Circuits and Systems,2008,(05):803-816.
  • 6H Asadi,M B Tahoori. Soft error modeling and prootection for sequential elements[A].Monterey,USA:IEEE Computer Society,2005.463-471.
  • 7D Holcomb,L Wenchao,S A Seshia. Design as you see FIT:System-level soft error analysis of sequential circuits[A].Nice,France:IEEE Computer Society,2009.785-790.
  • 8S J S Mahdavi,K Mohammadi. SCRA1P:Sequential circuits reliability analysis program[J].Microelectronics Reliability,2009,(07):924-933.
  • 9K Lingasubramanian,S Bhanja. Probabilistic error modeling for sequential logic[A].Hong Kong:IEEE Computer Society,2007.616-620.
  • 10K Lingasubramanian,S Bhanja. An error model to study the behavior of transient errors in sequential circuits[A].New Delhi,India:IEEE Computer Society,2009.485-490.

二级参考文献21

  • 1Kim J S, Nicopoulos C, Vijakrishnan N, et al. A probabilistic model for soft-error rate estimation in combinational logic[A]. Proc. of the 1 st Int' l Workshop on Probabilistic Analysis Techniques for Real Time and Embedded Systems, Pisa[C]. New York: Elsevier, 2034.25 - 31.
  • 2Asadi G, Tahoori M B. An analytical approach for soft error rate estimation in digital circuits[ A]. IEEE Int. Symp. on Circuits and Systems, Kobe [ C ]. Hoboken: John Wiley & Sons, 2005.2991 - 2994.
  • 3Krishnaswamy S, Viamontes G F, Markov I L, et al. Accurate reliability evaluation and enhancement via probabilistic transfer matrices[A]. Proc. of the Design, Automation and Test in Europe Conference and Exhibition, Munich[C ]. New York: ACM Society, 2005.282 - 287.
  • 4Parker K P and McCluskey E J. Probabilistic treatment of general combinational networks [J]. IEEE Trans on Computers, 1975,24(6) :668 - 670.
  • 5Parker K P and McCluskey E J. Analysis of logic circuits with faults using input signal probabilities[ J]. IEEE Trans on Computers, 1975,24(5) : 573 - 578.
  • 6Ogus R C. The probability of a correct output from a combinational circuit [ J ]. IEEE Trails on Computers, 1975,24 (5) : 534 - 544.
  • 7Zarandi H R, Miremadi S G, Ejlali A R. Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models[ A]. Proc. of the 18th IEEE Int'l Symp. on Defect and Fault-Tolerance in VLSI Systems, Boston[ C]. Washington De: IEEE Computer Society,2003.485 - 492.
  • 8Leveugle R., Cimonnet:D. ,Ammari A. System-Level Dependability Analysis with RT-Level Fault Injection Accuracy[ A]. 19th IEEE Int'l Symp. on Defect and Fault Tolerance in VLSI Systems, Cannes, France, 2004 [ C ]. Los Alamitos, California: IEEE Computer Society,2004.451 - 458.
  • 9Koren I. Signal reliability of combinational and sequential circuits[A].Proc.of the 7th Int'l Symp. on Fault-Tolerant Computing,Los Angeles[C]. Washington DC: IEEE Computer Society, 1977.162 - 167.
  • 10Kwek K H and Tohma Y. Signal reliability evaluation of self-checking circuits[A] .Proc. of the 10th Int'l Syrup. on Fault- Tolerant Computing, Kyoto[C]. Washington DC: IEEE Computer Society, 1980.257 - 262.

共引文献17

同被引文献89

引证文献12

二级引证文献27

电子学报
2013年 第1期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部