摘要
为了产生各种不同形式的脉冲宽度调制(PWM)信号,提出一种基于现场可编程门阵列(FPGA)的脉冲宽度调制信号发生器。采用硬件描述语言Verilog设计底层模块,并在FPGA芯片内部嵌入一个NiosII软核处理器,使用软硬件协同的工作方式产生多路PWM信号。实验结果表明,该信号发生器的频率输出范围为1 Hz-4 MHz,占空比可调范围为1%-99%,任意两路信号间的相位差范围为1°-180°,达到预期效果。
Aiming at solving problems such as how to generate various Pulse Width Modulation(PWM) signals,a PWM signal generator based on Field Programmable Gate Array(FPGA) is proposed in this paper.It uses Verilog to customize system peripherals,and a NiosII soft-core processor is embedded in the FPGA chip,which enables to generate multi-channel PWM signal through collaborative work of hardware and software.Experimental results show that the output range of its frequency is 1 Hz- 4 MHz,adjustable range of duty cycle is 1%-99%,and phase range between two signals is 1°-180°,achieving the desired effect.
出处
《计算机工程》
CAS
CSCD
2013年第2期260-264,269,共6页
Computer Engineering
基金
桂林电子科技大学信息科技学院与桂林亦元生现代生物技术有限公司合作基金资助项目(桂电W201111)
关键词
脉冲宽度调制
占空比
NIOSII软核
压控放大器
相位累加器
Pulse Width Modulation(PWM)
duty ratio
NiosII soft core
voltage controlled amplifier
phase accumulator