基于SDRAM的Bayer格式图像插值算法硬件设计

SDRAM Based Hardware Design of Bayer-pattern Demosaicking

针对传统的双线性Bayer格式图像彩色恢复算法效果不理想,提出了一种新算法,设计了一种将其用FPGA实现的硬件方案。改进算法应用梯度变化来增加通道间的相关性,提高线性插值的效果,根据探测器数据输出格式不满足Bayer插值算法要求,设计了一种基于SDRAM,运用乒乓操作和流水线等技术的硬件处理新机制。整个系统采用一片可编程门阵列(FPGA)作为硬件设计载体,使用Verilog-HDL硬件描述语言并采用自上而下的模块化设计对整个系统进行硬件描述。试验表明,算法在硬件上工作正常,实时输出的彩色图像在PSNR和目视方面均优于双线性插值算法。基本满足了系统在实时性和图像质量方面的要求。

An improved Bayer interpolation algorithm based on the FPGA is presented to solve the problems of traditional bilinear interpolation algo- rithm. Gradient difference which smooths the color differences is used to improve the interpolation algorithm. SDRAM combined with ping-pong operation and pipeline design is used to convert the Bayer format image captured from CMOS sensor to CFA format. One Field Programmable Gate Array （FPGA） is chosen as the hardware design platform,and the whole circuit is described with Verilog-HDL to perform the modularization design from top to bottom. Experimental results show that the algorithm works normally,real-time image obtained from the system indicates the algorithm can offer a higher PSNR and better visual effect than those of obtained from the Bilinear Interpolation algorithm. In conclusion the design meets the design requirement in real time and color image quality.