基于FPGA的UART实现

FPGA-Based Realization of UART

利用嵌入式技术,使用FPGA实现了多路全双工串口.该系统在接收端和发送端前都加一个具有8个缓冲单元的FIFO,实现内部模块时钟与串口速率匹配,同时,发送波特率和接收波特率等参数能够根据需要来进行相应的配置,并在Altera公司的CycloneIII系列FPGA硬件平台进行验证实验结果,该设计完全符合串口通信标准.

By aid of embedded technology, the Multi-channel full duplex serial port is realized by means of FPGA. This design has added an 8-buffer-cell FIFO in front of transmitting terminal and receiving terminal in order to achieve rate adapta- tion between the internal module clock and UART. Besides, the serial port baud rate can be set to cater for needs of different communication baud. The experimental results are subjected to verification on the hardware FPGA Cyclone Ⅲ platform of the Altera Company, which finds the design fully UART compatible.