期刊文献+

统一并行体系结构实验平台研制

Development of a union parallel architecture experimental platform
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摘要 介绍了计算机主流并行体系结构的发展,采用个人高性能计算机(personal high performance computer,PHPC)系统技术,研制了一种并行体系结构实验平台,介绍了其设计方案以及基于该实验平台的教学思路。该实验平台符合最新的"统一试验教学"理念,并具有便携性、灵活性、统一性、开放性以及先进性等特点。应用该实验平台可将计算机专业并行体系结构系列课程的课程内容、课程体系、专业教学大纲的要求纳入到一个统一的实验体系中,在保证可独立授课的基础上,通过实验内容间良好的衔接,实现相关课程教学的完整性。 The latest progress of mainstream computer parallel architecture is briefly reviewed. A union parallel architecture experimental platform is developed using personal high performance computer(PHPC) system technology. The experimental platform meets the latest union-teaching philosophy, and has the characteristics of portability, flexibility, uniformity, openness and progressiveness. The platform can incorporate the experi- ment requirements of different parallel architecture courses into a single experimental system, and achieve the integrity of the courses teaching.
出处 《实验技术与管理》 CAS 北大核心 2013年第2期62-65,69,共5页 Experimental Technology and Management
基金 国家“985工程”二期建设项目(985-2-104) 深圳大学科研基金资助面上项目201209
关键词 计算机系统结构 并行体系结构 PHPC 实验设备 FPGA computer architecture parallel architecture personal high performance computer experimental e- quipment FPGA
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