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A 27-mW 10-bit 125-MSPS charge domain pipelined ADC with a PVT insensitive boosted charge transfer circuit 被引量：3

A 27-mW 10-bit 125-MSPS charge domain pipelined ADC with a PVT insensitive boosted charge transfer circuit
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摘要 A low power 10-bit 125-MSPS charge-domain(CD) pipelined analog-to-digital converter(ADC) based on MOS bucket-brigade devices(BBDs) is presented.A PVT insensitive boosted charge transfer(BCT) that is able to reject the charge error induced by PVT variations is proposed.With the proposed BCT,the common mode charge control circuit can be eliminated in the CD pipelined ADC and the system complexity is reduced remarkably.The prototype ADC based on the proposed BCT is realized in a 0.18μm CMOS process,with power consumption of only 27 mW at 1.8-V supply and active die area of 1.04 mm^2.The prototype ADC achieves a spurious free dynamic range(SFDR) of 67.7 dB,a signal-to-noise ratio(SNDR) of 57.3 dB,and an effective number of bits(ENOB) of 9.0 for a 3.79 MHz input at full sampling rate.The measured differential nonlinearity(DNL) and integral nonlinearity (INL) are +0.5/-0.3 LSB and +0.7/-0.55 LSB,respectively. A low power 10-bit 125-MSPS charge-domain(CD) pipelined analog-to-digital converter(ADC) based on MOS bucket-brigade devices(BBDs) is presented.A PVT insensitive boosted charge transfer(BCT) that is able to reject the charge error induced by PVT variations is proposed.With the proposed BCT,the common mode charge control circuit can be eliminated in the CD pipelined ADC and the system complexity is reduced remarkably.The prototype ADC based on the proposed BCT is realized in a 0.18μm CMOS process,with power consumption of only 27 mW at 1.8-V supply and active die area of 1.04 mm^2.The prototype ADC achieves a spurious free dynamic range(SFDR) of 67.7 dB,a signal-to-noise ratio(SNDR) of 57.3 dB,and an effective number of bits(ENOB) of 9.0 for a 3.79 MHz input at full sampling rate.The measured differential nonlinearity(DNL) and integral nonlinearity (INL) are +0.5/-0.3 LSB and +0.7/-0.55 LSB,respectively.
作者 陈珍海 黄嵩人 张鸿 于宗光 季惠才
机构地区 Wide Bandgap Semiconductor Technology Disciplines State Key Laboratory China Electronic Technology Group Corporation School of Electronics and Information Engineering
出处 《Journal of Semiconductors》 EI CAS CSCD 2013年第3期112-120,共9页 半导体学报（英文版）
基金 supported by the National Natural Science Foundation of China(No.61106027) the 333 Talent Project of Jiangsu Province, China(No.BRA2011115)
关键词 pipelined analog-to-digital converter charge domain low power charge transfer circuit charge comparator pipelined analog-to-digital converter charge domain low power charge transfer circuit charge comparator
分类号 TN792 [电子电信—电路与系统]
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参考文献19

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同被引文献16

  • 1ALl A M A, MORGAN A, DILLON C, et al. A 16-bit 250-MS/s IF sampling pipelined ADC with Background calibration [ J ]. IEEE Journal of Solid-State Circuits, 2010, 45 (12): 2612-2613.
  • 2ALIA M A, DINC H, BI-IORASKAR P, et al. A 14 bit 1 GS/s RF sampling pipelined ADC with back- ground calibration [ J]. IEEE Journal of Solid-State Cir- cuits, 2014, 49 (12): 2857-2867.
  • 3FANG B N, WU J T. A 10-bit 300-MS/s pipelined ADC with digital calibration and digital bias generation [ J ]. IEEE Journal of Solid-State Circuits, 2013, 48 (3): 670-683.
  • 4YANG C Y, LI F L, LI W T, et al. An 85roW 14-bit 150 MS/s pipelined ADC with 71.3 dB peak SNDR in 130 nm CMOS [ C ] ff Proceedings of Asia Solid-State Circuits Conference. Singapore, 2013:85 -88.
  • 5SETTERBERG B, POULTON K, RAY S, et al. A 14b 2.5 GS/s 8-way-interleaved pipelined ADC with back- ground calibration and digital dynamic linearity correction [ C] // Proceedings of International Solid-State Circuits Conference. San Francisco, USA, 2013: 466-467.
  • 6ALIAMA, DINC H, BHORASKAR P, et. al. A 14 bit 1 GS/s RF sampling pipelined adc with background cali- bration [ J]. IEEE J Solid-State Circuits, 2014, 49 (12) : 2857-2867.
  • 7MIYAHARA Y, SANO M, KOYAMA K, et al. A14 bit 60 MS/s pipelined ADC adaptively cancelling opamp gain and nonlinearity [ J]. IEEE Journal of Solid- State Circuits, 2014, 49 (2): 416-425.
  • 8ANTHONY M, KOHLER E, KURTZE J, et al. A process-scalable low-power charge-domain 13-bit pipeline ADC [ C ] // Proceedings of Symposium on VLSI Cir- cuits. Honolulu, USA, 2008. 222-223.
  • 9CHEN Z H, QIAN H W, HUANG S R, et al. Low power time-interleaved 10-bit 250 MSPS charge domain pipelined ADC for IF sampling [J]. Journal of Semicon- ductors, 2013, 34 (6): 065005-1-065005-5.
  • 10张逸文,陈迟晓,余北,叶凡,任俊彦.A 14-bit 200-MS/s time-interleaved ADC with sample-time error calibration[J].Journal of Semiconductors,2012,33(10):116-121. 被引量：1

引证文献3

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Journal of Semiconductors
2013年 第3期

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