用于高速CMOS图像传感器的电容复用型循环ADC

A capacitor-reused cyclic ADC for high-speed CMOS image sensor

设计了一种用于高速CMOS图像传感器的列并行标志冗余位(RSD)循环式模/数转换器(ADC)。该ADC在每次循环中采样和量化输入信号同步进行,速度比传统的循环式ADC提高了1倍。利用电容复用技术,对于像素输出信号的相关双采样(CDS)操作和精确乘2运算,将仅使用1个运放和4组电容来实现,减小了芯片面积。通过0.18μm标准CMOS工艺完成了ADC电路设计和仿真。SPICE仿真结果表明,在4 MS/s的采样速度和1.8 V电源电压下,ADC的SNDR达到55.61 dB,有效位数为8.94 bit,功耗为1.34 mW,满足10 bit精度高速CMOS图像传感器系统的应用要求。

In this paper, a column parallel RSD cyclic ADC using capacitor-reused technique for CMOS image sensor is presented. With the capacitor-reused technique, the ADC samples and converts the signal simultaneously in each cycle of the conversion, and thus its conversion speed is twice that of the conventional cyclic ADC. In the proposed ADC, an amplifier and four groups of capacitors are used to complete the CDS and the accurate multiply-by-two operation, which results in great reduction in the area of capacitors. The presented ADC is designed and simulated in 0. 18 μm CMOS process using SPICE. The simulation results show that at a supply voltage of 1.8 V and a conversion rate of 4 MS/s, the designed ADC can achieve a SNDR of 55.61 dB and its power consumption is 1.34 mW.The ADC can satisfy 10 bit accuracy requirement of high-speed CMOS image sensor＇s application.