基于FPGA的DLMS自适应回波抵消滤波器实现

Implementation of an FPGA_Based DLMS Adaptive Filter for Echo Cancellation

传统的LMS算法结构不易于并行实现,而采用DLMS算法设计并行流水结构的自适应滤波器,使算法更适合在FPGA中的硬件实现。将DLMS自适应滤波器引入回波抵消设计中完成整体设计,并选取FPGA器件用硬件语言Ver-ilog HDL加以实现。通过仿真验证表明,该设计在抑制回波抵消方面具有良好的效果。

Based on the analysis of traditional LMS algorithm structure is not easy to be implemented in parallel, The DLMS algorithm is used to design a parallel pipeline structure adaptive filter to make the algorithm more suitable for hardware implementation in an FPGA. The DLMS adaptive filter is introduced to the whole echo cancellation design, after that, the Verilog HDL language is used to accom plish the design on the appropriate FPGA devices. Finally, the simulation results show that the design has good results in the suppression of the echo.