基于FPGA的FFT处理器设计

Design of FFT processor based on FPGA

针对现实生活中各种测试系统的需求,开发设计了能够分析多种系统特性的按时间抽取基2FFT处理器,在传统的FFT算法以及硬件单元分析的基础上,提出了一种新型蝶形运算方法,通过减少乘法运算以及采用查表法,加快系统运算速度。设计中采用8位有符号数完成256点数据处理,提出新的数据处理方式,避免了浮点运算为数据处理造成的困难,采用自顶向下的设计方法,用Verilog HDL编程实现各模块功能,并详细介绍了数据从外部读取后,经由存储到数据处理再到输出的完整过程,最后在FPGA上实现设计功能。

To meet the demands of all kinds of test systems, decimation in time Radix-2 FFT processor was designed to analyze characteristics of various systems. New butterfly-shaped operation method was proposed based on the traditional FFT algo- rithm and the analysis of hardware unit, which can reduce multiplication. And it adopted the Look-up table method so that the system speeds up. The design uses 8 words for data treatment of 256 points, and new method was established. At the same time, the top-down design method and Verilog HDL were used to realize the module functions. Finally, the entire process from reading to storing, processing and outputting was introduced, and the design was realized by using FPGA.