基于FPGA的高速并行DVB-S2标准LDPC译码

A FPGA-based High-Speed Parallel LDPC Decoder for DVB-S2 System

最新的CCSDS、DVB-S2等相关卫星标准都采用低密度校验(Low Density Parity Code,LDPC)码,其中DVB-S2中LDPC码由于码字长、码率多,不易于硬件实现。文章针对该码校验矩阵特性,给出一种基于改进最小和算法的高速并行译码器的FPGA实现方案。方案采用180并行,6bit位宽,在20次迭代下,基于Xilinx SC5VSX95T芯片的测试表明:设计方案支持200 MHz的时钟频率。

Low density parity code （LDPC） has been adopted by many standards in satellite communications, such as CCSDS, DVB-S2. For the LDPC used in DVB-S2, it is difficult to be realized due to its long code word and various code rates. In this paper, a high-speed parallel LDPC decoder is proposed for its FPGA realization by using the normalized sum- rate algorithm. With 180 parallels, 6 bit widths and 20 iterations, the decoder can support a frequency higher than 200 MHz according to our testing results in Xilinx SC5VSX95T.