期刊文献+

基于视频编解码的可重构处理器存储系统设计

Design of reconfigurable processor memory system for video codec
下载PDF
导出
摘要 针对可重构视频编解码处理器ReMAP-2在高清视频编解码应用中对大规模数据吞吐率的需求,提出一种由全双工的帧缓存器及直接内存存取(direct memory access,DMA)组成的高速存储系统.其中帧缓存器由2个4 kbyte存储器构成,每个存储器分为16个存储块,采用二维地址编码,通过数据排列开关对像素数据的重排序,可满足视频编解码算法对子块像素数据快速读取的需求.仿真实验表明。 A high-speed memory system is proposed for reconfigurable codec processor to access high data throughput rates in video codec applications. The full duplex frame buffer and direct memory access (DMA) are included in this new memory system. The frame buffer contains two memories with the size of 4 kbyte and is divid- ed into 16 banks. Two-dimensional address coding is introduced as well as data arrangement switch for fast sequen- tial data access by codec algorithm. The simulation result shows that the memory system can meet high perform- ance requirement for reconfigurable processor ReMAP-2 in high-definition video codec application.
出处 《深圳大学学报(理工版)》 EI CAS 北大核心 2013年第2期150-156,共7页 Journal of Shenzhen University(Science and Engineering)
基金 国家博士后基金资助项目(20110491091) 深圳市科技研发资金基础研究项目(JC201105160591A)~~
关键词 集成电路技术 可重构 处理器 数字信号处理 离散余弦变换 存储器 多媒体处理 视频编解码 integrated circuit technology reconfigurable processor digital signal processing discrete cosinetransform memory multimedia processing video codec
  • 相关文献

参考文献18

  • 1Khailany B, Dally W J, Kapasi U J, et al. Imagine media processing with streams [J]. IEEE Micro, 2001, 21 (2). 35-46.
  • 2Pham P, Mau P, Kim J, et al. An on-chip network fab- ric supporting coarse-grained processor array [ J]. IEEE transaction on Very Large Scale Integration (VLSI) Sys- tems, 2012, 21(1): 178-182.
  • 3Baumgarte V, Ehlers G, May F, et al. PACT XPP: a self-reconfigurable data processing architecture [ J]. The Journal of Supercomputing, 2003, 26(2): 167-184.
  • 4Singh H, Lee M H, Lu G, et al. MorphoSys: an inte- grated reconfigruable system for data-parallel and computa- tion-intensive applications [ J ]. IEEE Transactions on Computers, 2000, 49(5): 465-481.
  • 5Lattard D, Beigne E, Bernard C, et al. A telecom base- band circuit based on an asynchronous network-on-chip [ C]//IEEE International Solid-State Circuits Conference, Digest of Technical Papers. San Francisco (USA): IEEE Press, 2007: 258-601.
  • 6Vangal S, Howard J, Ruhl G, et al. An 80-tile 1.28 TFLPS network on-chip in 65 nm CMOS [ C ]//IEEE In- ternational Solid-State Circuits Conference, Digest of Tech- nical Papers. San Francisco (USA): IEEE Press, 2007 : 98-589.
  • 7Wentzlaff D, Griffin P, Hoffmann H, et al. On-chip in- terconnection architecture of the tile processor [J].IEEE Micro, 2007, 27 (5): 15-31.
  • 8Dai Peng, Wang Xin'an, Zhang Xing, et al. A high power efficiency reconfigurable processor for multimedia processing [ C ]// IEEE 8th International Conference on ASIC. Changsha (China): IEEE Press, 2009: 67-70.
  • 9Dai Peng, Wang Xin'an, Zhang Xing. A novel reconfigu- rable operator based IC design methodology for muhimedia processing [ C ]// 2009 IEEE Region 10 Conference (TENCON 2009). Singapore: IEEE Press, 2009 : 1-5.
  • 10戴鹏,雍珊珊,王新安,张兴.可重构视频编解码处理器ReMAP设计[J].北京大学学报(自然科学版),2011,47(3):418-426. 被引量:3

二级参考文献37

  • 1魏芳,李学明.基于MMX技术的H.264解码器优化[J].计算机工程与设计,2004,25(12):2218-2221. 被引量:6
  • 2Bobda C.可重构计算介绍[M].柏林:施普林格出版社,2007.8-9.
  • 3Rixner S.流处理器体系结构[D].波士顿:Kluwer学术出版社,2001.
  • 4Waingold E Taylor M Srikrishna D 等.将一切交给软件:Raw体系结构.计算机,1997,30(9):86-93.
  • 5虞志益 Meeuwsen M J Apperson R W 等.AsAP:异步处理器阵列.IEEE固相电路期刊,2008,43(3):695-705.
  • 6Khailany B Dally W J Kapasi U J 等.Imagine:流媒体处理.IEEE微体系结构,2001,21(2):35-46.
  • 7Hideharu Amano,Hasegawa Y,Tsutsumi S,等.MuCCRA芯片:可配置动态可重构处理器[C]//IEEE亚洲固相电路会议.济州岛(韩国):IEEE出版社,2007:384-387.
  • 8Baines R Pulley D.一种从各方面评估针对无线接收器基带处理的多个可重构架构的方法.IEEE通信杂志,2003,41(1):105-113.
  • 9Kyo S,Koga T,Okazaki S,等.一种具有51.2 GOPS、基于128个线性4路超长指令字运算单元、针对智能导航控制的可扩展视频识别处理器[C]..IEEE国际固体电路年会(ISSCC).旧金山:IEEE出版社,2003:1.48-49.
  • 10Goldstein S C Schmit H Budiu M 等 PipeRench.一种可雨构的结构及其编译器.计算机,2000,33(4):70-77.

共引文献5

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部