面向CSA算法的片上多核DSP处理器设计

Design of on-chip multicore DSP processor for chirp-scaling algorithm

在近几十年中,雷达成像的功能已经在国内外获得了广泛的关注和应用。为了较高效率完成CSA算法的实现,本设计充分利用CSA算法软件编程的特点,采用了片上多核阵列作为专用处理部件,并且采用两级仲裁和回环数据的路径配置方式形成可重构的数据通路,增加了数据通信带宽和函数执行的并行性,实验数据表明该设计方案能够在CSA算法的应用中达到最高接近32倍的加速比,可以有效地提升单片雷达信号处理的能力。

In the recent decades, radar imaging function has obtained wide attention and application. In order to implement the CSA algorithm with higher efficiency, the design takes full advantage of the characteristics of the CSA algorithm with the implantation of multi-cores on chip as a specific processing unit. Two-stage arbitration and loopback data path form a reconfigurable data path, increasing the data bandwidth and the parallelism of the execution of functions. The experiment results show that the design can achieve up to 32 times speed up in the CSA algorithm, which can efficiently improve the performance of the radar signal processing of a single-chip.