提高SoC硬件系统验证效率方法的综述(英文)

Review on Productivity Improvement of SoC Hardware Verification

随着片上系统(SoC)设计复杂度的增加,芯片设计和验证之间的差距逐渐拉大。如何提高验证效率成了集成电路业面临的一个巨大挑战。该文回顾了近年来面向这一挑战的国内外研究工作,提出了一个新的验证范例——边设计边验证。该方法结合结构化设计和递归式验证,用于缓解验证的负担。同时,还提出了实现该方法的基本要素,用于指导未来的研究。

As system on chip （SoC） design complexity explodes, the gap between chip design and verification has been widened. How to improve verification productivity represents a great challenge to the IC industry. Recent efforts in addressing this challenge are reviewed and then a new verification paradigm, verification-while-designing, is proposed. This methodology combines hierarchical design and recursive verification, aiming at releasing the verification challenge. The fundamental points enabling the methodology are also outlined.