期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

高速PCB上同步开关噪声抑制的多级电容法 被引量：2

Method for the Suppression of Simultaneous Switching Noise with Multi-stage Capacitors in High-Speed PCB
下载PDF
导出
摘要 基于微波网络理论,研究了同步开关噪声的传播与抑制,提出了一种新的抑制噪声传播的多级电容法,研究表明该方法采用多列分布电容和增大噪声路径传输损耗能够有效地抑制噪声的传播,提高电容噪声抑制的效率。通过FDTD仿真和测试结果验证了该方法的有效性,并给出了多级电容法抑制噪声的应用规则。 The transmission and suppression of the simultaneous switching noise （SSN） are investigated based on microwave network principle. A new method for the suppression of the noise transmission with multi-stage capacitors is presented in this paper. The design rules of the method with multi-stage capacitors are derived. The simulation results show that using the multi-row distributed capacitors and increasing transmission loss of noise path could improve the ability to suppress the noise transmission and increase the efficiency of the noise suppression with capacitors. Finally, the performance of the method is verified with finite difference time domain（FDTD） simulations and measured results.
作者 曲咏哲 李玉山 丁同浩 闫旭
机构地区 西安电子科技大学电路CAD研究所
出处 《电子科技大学学报》 EI CAS CSCD 北大核心 2013年第2期229-233,共5页 Journal of University of Electronic Science and Technology of China
基金 国家自然科学基金(60672027 60871072) 教育部博士点基金(20050701002)
关键词 电容 时域有限差分 电源 地平面 同步开关噪声 传输损耗 capacitor finite difference time domain（FDTD） power/ground plane simultaneousswitching noise （SSN） transmission loss
分类号 TN401 [电子电信—微电子学与固体电子学]
  • 相关文献

参考文献12

  • 1WANG C C, KUO C W, WU S M, et al. A novel time-domain approach for extracting broadband models ofpower delivery networks with resonance effect[J]. IEEE Trans Advanced Packag, 2009, 32(3): 636-643.
  • 2ZOU G P, WEI X C, LIE P, et al. Modeling of the simultaneous switching noise in high speed electronic circuit with the integral equation method and vector fitting method[J]. IEEE Trans Magnetics, 2011, 47(5): 1490-1493.
  • 3尚玉玲,李玉山.高速互连渐进式串扰故障激励测试模型研究[J].西安电子科技大学学报,2009,36(2):314-321. 被引量：2
  • 4KIM H, JEONG Y, PARK J, et al. Significant reduction of power/ground inductive impedance and simultaneous switching noise by using embedded film capacitor [C]//Electrical Performance of Electronic Packaging. New Jersey: IEEE, 2003.
  • 5HUBING T, CHEN J, DREWNIK J, et al. Power bus noise reduction using power island in printed circuit board designs[C]//Electromagnetic Compatibility, 1999 International Symposium on. Tokyo: IEEE, 1999.
  • 6WU T L, CHEN S T, HUANG J N, et al. Numerical and experimental investigation of radiation caused by the switching noise on the partitioned de power/ground-planes of high-speed digital PCB[J]. IEEE Trans Electromagnetic Compatibility, 2004, 46(1): 33-45.
  • 7ZEEFF T M, HUBING T H. Reducing power bus impedance at resonance with lossy components[J]. IEEE Trans Advanced Packag, 2002, 25(2): 307-310.
  • 8KWOM J H, SIM D U, KWAK S II, et al. Novel electromagnetic bandgap array structure on power distribution network for suppressing simultaneous switching noise and minimizing effects on high-speed signals[J]. IEEE Trans Electromagnetic Compatibility, 2010, 52(2): 365-372.
  • 9WANG T K, HSIEH C Y, CHUANG H H, et al. Design and modeling of a stopband-enhanced EBG structure using ground surface perturbation lattice for power/ground noise suppression[J]. IEEE Trans Microwave Theory Tech, 2009, 57(8): 2047-2054.
  • 10KIM T H, SWAMINTHAN M, ENGIN A E, et al. Electromagnetic band gap synthesis using geneticn algorithms for mixed signal applications[J]. IEEE Trans Advanced Packag, 2009, 32(1): 13-25.

二级参考文献13

  • 1Kim Yongjoon,Yang Myunghoon, Park Youngkyu. An Effective Test Pattern Generation for Testing Signal Integrity [C]//Proceedings of the 15th Asian Test Symposium. Washington: IEEE Computer Society, 2006: 279-284.
  • 2Attarha A, Nourani M. Test Pattern Generation for Signal Integrity Faults on Long Interconnects [C]//Proceedings 20th IEEE VLSI Test Symposium. Washington: IEEE Computer Society, 2002: 336-241.
  • 3Yungseon E, Eisenstad W R, Ju YoungJeong, et al. A New On-chip Interconnect Crosstalk Model and Experimental Verification for CMOS VLSI Circuit Design[J]. IEEE Trans on Electron Devices, 2000, 1(47):129-140.
  • 4Cuviello M, Dey S, Bai Xiaoliang. Fault Modeling and Simulation for Crosstalk in System-on-chip Interconnects [C]// IEEE/ACM International Conference on Computer-Aided Design. CA: IEEE Computer Society, 1999: 297-303.
  • 5Cao Yu, Huang Xuejue, Chang N H, et al. Effective On-chip Inductance Modeling for Multiple Signal lanes and Application to Repeater Insertion[J]. IEEE Trans on Very Large Scale Integration Systems, 2002, 6(10): 799-805.
  • 6Tehranipour M H, Ahmed N, Nourani M. Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity [C]//IEEE International Conference on Computer Design: VLSI in Computers and Processors. CA: IEEE Computer Society, 2003: 554-559.
  • 7Che Nansen. Modeling of Nonideal Return Paths on Multilayer Package [C]//52nd Electronic Components and Technology Conference. CA: IEEE Components, Packaging and Manntfacturing Technology Society, 2002: 57-61.
  • 8Azad N. Analytical Models for Coupled Distributed RLC Lines with Ideal and Non-ideal Return Paths [C]//Technical Digest-lnternational Electron Devices Meeting. Washington: IEEE Electron Devices Society, 2001: 689-692.
  • 9Sekine T. A Lossy Interconnect Modeling in Both the Time and the Frequency Domain Using a Synthesis Method of Lossy Nonuniform Transmission Line [C]//18th International. Zurich Symposium on EMC. ETH Zurich: LAboratory for Electromagnetic Fields and Microwave Electronics, 2007: 65-68.
  • 10Grivet-Talocia S. Adaptive Transient Solution of Nonuniform Multiconductor Transmission Lines Using Wavelets [J]. IEEE Trans on Antennas and Propagation, 2000, 10(48): 1563-1573.

共引文献1

同被引文献25

引证文献2

二级引证文献13

电子科技大学学报
2013年 第2期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部