摘要
针对SRAM(Static Random Access Memory)型FPGA单粒子翻转引起软错误的问题,该文分析了单粒子单位翻转和多位翻转对布线资源的影响,提出了可以减缓软错误的物理设计方法。通过引入布线资源错误发生概率评价布线资源的软错误,并与故障传播概率结合计算系统失效率,驱动布局布线过程。实验结果表明,该方法在不增加额外资源的情况下,可以降低系统软错误率约18%,还可以有效减缓多位翻转对系统的影响。
To solve the problem of soft error caused by Single Event Upset （SEU） in Static Random Access Memory （SRAM）-based Field Programmable Gate Arrays （FPGAs）, the impact of routing resources by Single Bit Upset （SBU） and Multiple Bit Upset （MBU） is analyzed. A new method of soft-error-mitigation physical design approach is presented. In the approach, the error probability of routing resources is introduced for evaluation soft error. Combined with error propagation probability, system failure rate is calculated for driving placement and routing. The experimental results show that the system failure rate decreases about 18% using proposed method. This method can also effectively mitigate effect of multiple bit upset.
出处
《电子与信息学报》
EI
CSCD
北大核心
2013年第4期994-1000,共7页
Journal of Electronics & Information Technology
关键词
现场可编程门阵列
布局布线
软错误
单粒子翻转
多位翻转
Field Programmable Gate Arrays （FPGA）
Placement and routing
Soft error
Single Event Upset（SEU）
Multiple Bit Upset （MBU）
