16位嵌入式RISC微处理器设计

Design of 16 bit embedded RISC microprocessor

设计了一款具有4级流水线结构的16位RISC嵌入式微处理器。针对转移指令,未采用惯用的延迟转移技术,而是通过在取指阶段增加相应的硬件结构实现了无延迟转移。采用内部前推技术解决了指令执行过程中的数据相关。同时通过设置相应的硬件堆栈实现了对中断嵌套和调用嵌套的支持。整体系统结构采用VerilogHDL语言设计,指令系统较完善。在软件平台上的仿真验证初步表明了本设计的正确性。

Designed a four pipeline structure of the 16-bit RISC embedded microprocessor. For the branch instruction, did not adopt the delayed branch technology which is commonly used, but by adding the appropriate hardware structures to achieve branch without delay. Using the internal forwarding technology to solve data hazard during the instruction execution process. The microprocessor supported interrupts nesting, calls nesting by adding hardware stacks. The system was programmed by Verilog HDL, and has a relatively complete instruction system. Finally, simulation on the software platform indicated the correctness of the design preliminarily.