基于PD SOI工艺的高压NMOS器件工艺研究

Study of HVNMOS Device Based on PD SOI Process

由于PD SOI工艺平台的特殊性,P阱浓度呈现表面低、靠近埋氧高的梯度掺杂。常规体硅的高压N管结构是整个有源区在P阱里的,需要用高能量和大剂量的P注入工艺将漂移区的P阱反型掺杂,这在工艺上是不容易实现的。文章针对常规高压NMOS器件做了仿真,发现漂移区必须采用能量高达180 KeV、剂量6×1013以上的P注入才能将P阱反型,形成高压NMOS器件,这在工艺实现上不太容易。而采用漂移区在N阱里的新结构,可以避免将P阱上漂移区反型的注入工艺,在工艺上容易实现。通过工艺流片验证,器件特性良好。

Because of particularity of PD SOI process, the concentration of P well appears a gradually increase from surface to BOX. In a normal high voltage NMOS device, an implant process of P element with great energy and dose must be needed, it is difficult to realize. A simulation of normal high voltage NMOS device has been accomplished based on PD SOI process. In order to invert the drift region in P well and form NMOS device, P should implanted with high energy （above 180 KeV） and high dose （above 6×10^13） . This is not an easy way in process. But it is much easier to adopt a new structure, that the drift region is in N well. Verified by manufacturing, the character of the new structure device is good.