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硅基不同晶面上的空穴迁移率研究 被引量:1

Hole Mobility Measured on Silicon with Different Crystalline Orientations
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摘要 近年来,金属氧化物半导体场效应晶体管(MOSFET)的特征尺寸减小并进入纳米尺度,为了改善器件的短沟道效应,器件由原来的平面结构改为立体结构。而在立体结构器件中,沟道由不同于传统Si(100)晶面的Si晶面所组成。因此,为了了解不同Si晶面上器件反型层空穴迁移率的变化情况,在不同晶面Si衬底上分别制作了pMOSFET,并研究了器件的空穴迁移率。采用Split C-V方法测试了Si(100),(110),(111)和(112)晶面上器件的空穴迁移率。结果表明,Si(110)晶面上的空穴迁移率最大,Si(112)晶面上<111>沟道方向空穴迁移率比(110)晶面上空穴迁移率小,而略大于(100)和(111)晶面上的空穴迁移率,(100)晶面上的空穴迁移率最小。 The feature size of the metal oxide semiconductor field effect transistors (MOSFETs) decreases and has reached the nanometer scale in recent years. In order to improve the short channel effects ( SCE), MOSFETs are evolved from a planar structure to a three-dimensional structure. However, in the three-dimensional structure, the channels are often composed by two or three silicon surfaces with different crystalline orientations from the conventional (100) silicon orientation. Therefore, in order to understand the impact of different crystalline orientations on hole mobility in inversion layers on silicon, pMOSFETs were fabricated on silicon substrates with various crystalline orientations and were characterized. Hole mobility was measured using the split C-V test method in pMOSFETs on ( 100), (110) , (111) and (112) silicon substrates. Hole mobility of (110) silicon is found to be the largest. Hole mobility in 〈 111 〉 channel direction on (112) silicon is smaller than that on (110) substrate and slightly larger than that on (100) and ( 111 ) silicon substrates. The hole mobility on (100) silicon is found to be the smallest.
出处 《半导体技术》 CAS CSCD 北大核心 2013年第4期297-301,共5页 Semiconductor Technology
基金 国家重点基础研究发展计划(973计划)资助项目(2011CBA00605) 中国科学院百人计划
关键词 空穴迁移率 晶面 沟道方向 有效电场 Si(112)晶面 hole mobility crystalline orientation channel direction effective electrical field (112) silicon
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  • 1YANG M, CHAN K, SHI L, et al. Hybrid-orientation technology (HOT): opportunities and challenges [ J]. IEEE Transactions on Electron Devices, 2006, 53 (5) : 965 - 978.
  • 2AUTH C, CAPPELLANI A, CHUN J S, et al. 45 nm High-k + metal gate strain-enhanced transistors [ C] // Proceedings of Symposium on VLSL Technology. Honolulu, USA, 2008 : 128 - 129.
  • 3YANG H S, MALIK R, NARASIMHA S, et al. Dual stress liner for high performance sub-45 nm SOl CMOS manufacturing [ C ] // Proceedings of International Electron Devices Meting. San Francisco, USA, 2004: 1075 - 1077.
  • 4LIAO W S, LIAW Y'G, TANG M C, et al. PMOS hole mobility enhancement through SiGe conductive channel and highly compressive ILD-SiN, stressing layer [J]. IEEE Electron Devices Letters, 2008, 29 ( 1 ) : 86 - 88.
  • 5YANG M, IEONG M, SHI L, et al. High performanceCMOS fabricated on hybrid substrate with different crystal orientations [ C] // Proceedings of International Electron Devices Meting. Washington, USA, 2003 : 453.
  • 6MEREU B, ROSSEL C, GUSEV E P, et al. The role of Si orientation and temperature on the carrier mobility in metal oxide semiconductor field-effect transistors with ultrathin HfO2 gate dielectrics [ J]. Journal of Applied Physics, 2006, 100 (1): 014504-1-014504-6.
  • 7KUTSUKI T, SHIMIZU K, NOMURA H, et al. Experimental investigation on direction dependence of Si (100) and Si (110) hole mobility in ultra-thin body pFETs [ C] // Proceedings of Ultimate Integration on Silicon. Grenoble, France, 2012:85 - 88.
  • 8CHAO T S, LIN Y H, YANG W L, et al. Mobility enhancement of MOSFETs on p-silicon ( 111 ) with In situ HF-vapor pre gate oxide cleaning [ J ]. IEEE Electron Device Letters, 2004, "25 (9) : 625 - 627.
  • 9LIME F, OSHIMA K, CASSE M, et al. Carrier mobility in advanced CMOS devices with metal gate and HfO2 gate dielectric [ J]. Solid State Electronics, 2003, 47 (10) : 1617 - 1621.
  • 10TAKAGI S, TORIUMI A, IWASE M, et al. On the universality of inversion layer mobility in Si MOSFET' s : part I-effects of substrate impurity concentration [J]. IEEE Transactions on Electron Devices, 1994, 41 (12) : 2357 -2362.

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