一种基于FPGA的芯片测试多通道串口扩展设计

Multi-channel serial port expansion design used in chip testing based on FPGA

为了满足智能卡芯片的测试需求,在降低测试成本、提高测试速度的基础上,给出了一种在FPGA上实现的芯片测试的多通道串口扩展器设计,主要包括仲裁器设计、多路选择器以及显示译码器的设计。FPGA采用EP1C12Q240C8,利用状态机实现仲裁器,并改进了仲裁器电路结构,以提高扩展器工作速度,且结构简单,面积小。数据选择器以及显示译码器采用组合逻辑实现。利用Modelsim分别对加busy判断的轮换仲裁,以及状态机实现的仲裁进行仿真。实验和应用结果表明了设计的有效性,并且状态机仲裁提升了系统的性能。

In order to meet the testing requirements of the smart card chip, such as reduce test costs and improve test speed, this paper gives a design of multi-channel serial port expander used in chip testing based on FPGA,including the design of the arbiter,multiplexer and decoder. FPGA is EPIC12Q240CS. In order to improve the operating speed of the expander,this paper makes use of state machine to achieve the arbiter and improve the circuit configuration of the arbiter. Meanwhile, the expander has simple structure and small size. The data selector and display decoder are implemented by combination logic circuit. Making use of Modelsim to simulate the rotation arbitration added busy judgment and the arbitration implemented by state machine respectively. The experiments and the results have showed the effectiveness of the design and the state machine has enhanced the performance of the system arbitration.