基于FPGA-IP Core的64阶FIR滤波器的设计

Design of 64 order FIR filter based on FPGA-IP Core

在电子信息技术迅猛发展的当代,基于专用集成芯片的传统模拟开发模式已渐渐不能跟上无线电通信技术的前进脚步,宽带化和数字化成为时下电子技术的主流[1]。本设计充分利用FPGA的强大功能及有限冲击波响应线性相位的优势,在ISE软件环境下,通过Verilog HDL这款硬件描述语言来进行高速FIR数字滤波器的逻辑设计。仿真结果表明结果符合理论期望值,验证了此种优化的滤波器方法先进、工作速度快,更能大大地节省硬件资源,所以总体性能优于传统方式的FIR滤波器。

In the contemporary when witnesses a rapid improvement of electronic information technology,the development of traditional analog model based on specific integrated chip has gradually unable to keep up with the advanced steps of the radio communication technology. Broadband and digitization currently become the mainstream of electronic technolo- gy. The design take full advantage of the powerful role of FPGA and the superiority of linear phase of Finite Impulse Re- sponse,accomplish the logical design of high-speed digital FIR filter under the environment of ISE software through Ver- ilog HDL which is a kind of hardware description language. The simulation results show that the consequences in line with theoretical expectations, which verify that the optimized filter possess advanced method as well as fast work speed, what＇s more,it greatly saves hardware resources. For these reason its overall performance is more preferential than the FIR filter in traditional way.