圆片级封装垂直通孔引线寄生电容研究

The Study on the Parasitic capacitance of Wafer-level packaging vertical feedthrough

垂直通孔引线是圆片级封装方法的关键技术之一。针对玻璃衬底垂直通孔引线技术,本文就通孔引线寄生电容开展了研究。首先,利用Ansoft Maxwell 3D对其寄生电容进行了建模和模拟仿真,研究了不同通孔底面直径(d)、玻璃衬底厚度(t)和通孔中心间距(g)的影响。其次,基于微加工工艺,制备了圆片级玻璃衬底的垂直通孔引线样品。最后,对实验加工样品电容进行测试,并与模拟结果进行了比较与分析。

Vertical feedthrough is one of important techniques for wafer - level packaging technology. Its parasitic capacitance based on the glass substrate is studied in this essay. At first, we simulated the para- sitic capacitance by Ansoft Maxwell 3 D and analyzed the effect of different diameters of holes, glass thick- ness and holes gap. Secondly, vertical feedthroughs were fabricated by microfabrication technology. At last, we measured their capacitances and compared with simulation results.