极低电源电压和极低功耗的亚阈值SRAM存储单元设计

An ultra-low-supply-voltage ultra-low-power subthreshold SRAM bitcell design

提出一款可以工作在极低电源电压条件下,功耗极低的亚阈值SRAM存储单元.为使本设计在极低电源电压(200 mV)条件下依然能够保持足够的鲁棒性,采用差分读出方式和可配置的操作模式.为极大限度地降低电路功耗,采用自适应泄漏电流切断机制,该机制在不提高动态功耗与不增加性能损失的前提下,可同时降低动态操作(读/写操作)和静态操作时的泄漏电流.基于IBM 130 nm工艺,实现了一款256×32 bit大小的存储阵列.测试结果表明,该存储阵列可以在200 mV电源电压条件下正常工作,功耗(包括动态功耗和静态功耗)仅0.13μW,为常规六管存储单元功耗的1.16%.

An ultra-low-supply-voltage ultra-low-power subthreshold static random access memory （SRAM） bitcell with a self-adaptive leakage current cutoff scheme is proposed for ultra-low-supply- voltage （200 mV） applications. To achieve enough robustness in those supply voltage, the differen- tial sensing method and the reconfigurable operating mode are adopted. With self-adaptive leakage current cutoff scheme, the proposed design can reduce the leakage current of dynamic and static op- eration without increasing the dynamic energy consumption and the performance loss. A 256 × 32 bit SRAM array is fabricated based on IBM 130 nm CMOS technology. And testing results demonstrate that the total power （ dynamic power and standby power） consumption of SRAM at 200 mV is 0.13μW which is only 1.16% of conventional 6T SRAM.