QC-LDPC码编码器的FPGA实现

FPGA Implementation for Encoder of QC-LDPC Codes

准循环低密度奇偶校验(QC-LDPC)码具有优异的纠错性能,已被纳入空间数据系统咨询委员会(CCSDS)的近地轨道通信标准。分析了QC-LDPC码的特点,提出一种基于生成矩阵的编码方法。该方法利用循环矩阵特性简化生成矩阵的存储模式,减少了资源消耗,同时利用循环移位寄存器和累加器实现矩阵乘法,降低了编码算法复杂度。在Xilinx xc4vsx55 FPGA上,采用VHDL语言实现了CCSDS标准中(8176,7154)LDPC编码器的设计。仿真结果表明,设计的编码器资源占用较少,吞吐量约为228 Mbit/s。

QC - LDPC code possesses excellent property of error correction, and has been included in the Near-earth orbit communication standard which is proposed CCSDS. This paper analyzed the properties of QC - LDPC and proposed an encoding method based on generator matrix. This encoding method simplifies the storage pattern of generator matrix through circulant matrix property, thus lessens the resource con- sumption. Also, it realizes the matrix multiplication by the utilization of cycle shift register and accumula- tor, and then reduces the complexity of encryption algorithm. Based on Xilinx xc4vsx55 FPGA, use VHDL language, the design of （8176, 7154） LDPC encoder in the C CSDS standard is realized. Simula- tion results show that this encoder occupies less resource, and has a throughput about 228 Mbit/s.