一款DSP指令集模拟器性能优化技术研究

Research on Optimization Techniques of Instruction Set Simulator for ZW100 DSP

文中研究和设计的指令集模拟器(Instruction Set Simulator,ISS)仿真了"中微一号"(ZW100)DSP指令系统和存储器系统行为。在现代嵌入式系统设计过程中,ISS能够在硬件原型构造出来之前,完成对处理器设计的正确性验证和性能分析工作;同时,其还可用于验证操作系统、编译器、汇编器、连接器等系统软件的正确性和各项性能指标。目前,国内外对ISS的研究主要集中在保证ISS灵活性的前提下,应用各种优化技术,提升它的指令仿真执行速度。文章在吸收借鉴目前国际上关于ISS性能优化技术的基础上,通过对仿真策略、仿真内存管理、二进制指令译码算法进一步优化,提高了ISS的整体性能。实验证明,文中提出的优化技术能够有效提升ISS的性能。

This paper concentrates on the instruction-accurate Instruction Set Simulator （ISS） which simulates the CPU and main memory of the ZWIO0 DSP chip. In the modem embedded system design process, ISS can help to validate the processor which does not yet exist, as well as the compiler design, the operating system design, the performance test etc. At present, the research of the ISS is concentrated on improving the simulator speed on the condition of its flexibility. This paper aims to optimize the simulate speed. Based on the general optimization techniques, improves the performance of ISS by the optimization of simulate strategy, memory management and decode algorithm. It has been tested that the optimization strategies of this paper can improve the performance of ISS.