GSM的下行同步算法设计与FPGA实现

Design and implementation of GSM downlink synchronization based on FPGA

本文在分析GSM通信系统中小区初始搜索中的定时同步原理的基础上,提出了一种基于FFT的GSM下行同步算法和FPGA实现GSM粗同步和精同步的高实时性实现方案,并使用Modelsim和MATLAB对算法的正确性进行了仿真验证;最后在Altera Cyclone III FPGA硬件平台进行了板级调试和实时数据验证,结果表明该同步算法切实可行且实时性好、稳定度高。

On the base of analyzing the theory of synchronization of GSM systems in the initial cell search,this paper puts forward one downlink synchronization algorithm of GSM based on FFT and high realtime performance concrete implementation scheme using FPGA to realize GSM coarse synchronization and fine synchronization.Then this paper uses Modelsim and MATLAB simulating the program to verify algorithm correctness.Finally it finishes the debugging on board of Altera Cyclone III FPGA chip to verify the real-time data,and the result shows the synchronization algorithm feasible,more real-time and higher stability.