一种用于E1/T1接口电路的全数字锁相环

An All Digital Phase Locked Loop for E1/T1 Interface Circuits

提出了一种直接实现的一阶全数字锁相环时钟提取电路 ,通过鉴相窗口拓宽、高倍采样、噪声滤波、输出相位累加器比特泄漏等改进算法 ,使电路完全能满足 AT&T和 ITU标准规定的相位抖动传递函数和输入抖动容限的要求。该电路具有简单、实用。

A first order all digital phase locked loop based E1/T1 c lock and data recovery circuit is presented in the paper, which can fully meet the AT&T and ITU recommendations and standards on jitter transfer and input jitt er tolerance by using novel algorithms, such as expanded sample window, high speed sample rate, noise smoothing filter as well as output phase accumulator leakage The circuit is simple, versatile, and suitable for VLSI design