无污染Cache访问控制技术

Non-polluting cache accessing technique

制造工艺的快速进步给集成电路设计提供了广阔的空间,而发展较慢的设计能力导致难以对片上资源高效利用。目前,高性能处理器片上Cache普遍占到芯片总面积的一半以上,而如何高效、智能地利用片上Cache空间,构建高性能存储系统是处理器微体系结构研究的重要内容。分析了Cache数据污染和猜测执行对处理器性能的影响,并在此基础上提出一种基于数据Tag有效位分裂的无污染Cache访问控制技术—Pease,将原先D-CacheTag中的一位数据有效位扩展为读数据有效位（RVB）和写数据有效位（WVB）两位,根据RVB和WVB值的不同组合对数据读写访问进行控制。不但充分保留了猜测执行的数据预取性,使污染数据透明化,写入数据时无需对污染数据进行替换操作,消除了污染数据对Cache效率的影响。Pease技术相对于baseline结构来说,IPC的提升幅度为1.05%~8.40%,平均提升4.04%;L1 D-Cache缺失率降低幅度为19.05%~48.16%,平均降低29.66%。

Rapid progress of semiconductor fabrication provid-es capacious space for IC designs, but unfortunately, the slow development of design ability makes it difficult to utilize the on-chip resource efficiently. At present, more than half of die area of modern microprocessor is inhabited by cache. So, how to make use of cache space smartly and efficiently, and construct high performance memory system has become one of the most important content in processor architecture design. This paper analyses the impacts of cache data pollution and speculative execution to processor performance, and proposes a non-polluting cache accessing technique based on data tag valid-bit splitting, which is called Pease. The valid-bit in D-Cache tag is splited into two bits, read data valid bi（tRVB）and write data valid bi（tWVB）. According the different RVB and WVB combinations, corresponding accessing strategies to D-Cache are applied. As a result, Pease technique not only preserves the prefetch ability of speculative execution, but also makes the cache polluting data transparent, which means that, in no empty cache line situation, consequent data can be written into D-Cache directly, but without need to perform cache replacement operation. In other word, Pease technique makes polluting data totally harmless to D-cache. Simulation result indicates that, relative to the baseline architecture, Pease technique improves IPC from 1.05% to 8.40% , averagely 4.04% , and reduces miss rate of D-Cache from 19.05% to 48.16% averagely 29.66%.