支持推测并行化的事务存储硬件模拟系统

Hardware Simulation System for Transactional Memory with Speculative Parallelization

多核处理器通过增加处理器核数提高计算能力,虽然可以通过同时运行多道程序的方式利用处理器资源,但是多核处理器真正的成功取决于解决并行应用开发中的难题.为此,处理器体系结构和编程模型的协同开发是必须的.而随着核数的增多,传统上使用的软件模拟器因为软件的串行性而性能越来越差,无法支持这种软硬件协同开发.FPGA天生的并行性使它在模拟多核处理器时具有较高的模拟性能和高度的可扩放性,成为处理器体系结构研究的理想工具.本文介绍了基于FPGA的多核模拟系统,RAMP-Pink.该系统基于HASim实现,同时支持事务存储和线程级推测,用于对事务存储和线程级推测的软硬件协同开发.该模拟系统可配置不同的FPGA开发平台,也可以以软件模拟方式运行.

Multi-core processor provides computing ability by integrating more and more processor cores. Although we can utilize chip multi-processor cores by running many programs concurrently, parallel programming is more important for speeding up one single program. Indeed, the practical success of chip-multiprocessors consists in addressing the difficulties of parallel programming. To this end, it is necessary to co-develop new architectures with novel programming models. As the number of integrated on-chip cores is getting larger and larger, software simulator is no longer a practical environment for interesting experiments of chip multi-processor, due to the serial characteristic of software. As an alternative, FPGA-based simulation platform has become the optimal platform for this research, because of their inherent parallel characteristics. In this paper, we present the RAMP-Pink simulation system based on FPGA. This simulation system, which supports both Transactional Memory and Thread Level Speculation, is based on HASim simu- lation framework, and can be used for architecture and programming model co-development. In addition, our designed system can be configured with different FPGA development platform and also can run in software mode.