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Impactof Device Architecture on Performance and Reliability of Deep Submicron SOI MOSFETs( invited paper) 被引量:7

Impact of Device Architecture on Performance and Reliability of Deep Submicron SOI MOSFETs (invited paper)
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摘要 The main electrical properties of advanced Silicon On Insulator MOSFETs are addressed. The subthreshold and high field operations are analysed as a function of device architecture. The special SOI parasitic phenomena, such as the floating body potential and temperature, are critically reviewed. The main limitations of submicron MOSFET are comparatively evaluated for various SOI structures. Short channel and hot carrier effects as well as the reliability of the SOI technology are investigated for gate length down to sub\|0 1 micron. The main electrical properties of advanced Silicon On Insulator MOSFETs are addressed. The subthreshold and high field operations are analysed as a function of device architecture. The special SOI parasitic phenomena, such as the floating body potential and temperature, are critically reviewed. The main limitations of submicron MOSFET are comparatively evaluated for various SOI structures. Short channel and hot carrier effects as well as the reliability of the SOI technology are investigated for gate length down to sub\|0 1 micron.
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2000年第10期937-954,共18页 半导体学报(英文版)
关键词 SOI MOSFET 体系结构 可靠性 MOSFET SOI deep submicron performance reliability
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参考文献6

  • 1Cristoloveanu S,Electrical Characterization of Silicon-On-Insulator Materials and Devices,1995年
  • 2Su L T,IEDM Tech Dig,1992年,357页
  • 3Fossum J G,Proc IEEE Int SOI Conference,1992年,132页
  • 4Xia Yongwei,半导体学报,1990年,11卷,12期,962页
  • 5Chen C E D,IEEE Electron Dev Lett,1988年,9卷,636页
  • 6Wang Shouwu,半导体学报,1985年,6卷,3期,225页

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