摘要
提出了异构多核图形处理器(HMGPU)存储管理系统的硬件实现方法,采用固定分区与分页式分区两种方式分别对大片连续数据与小片非连续数据进行管理,使用Verilog语言进行硬件设计和仿真,并在FPGA开发板上进行了验证。实验结果表明,该系统为HMGPU提供了2 021.2 MB/s的有效存储带宽。
A hardware method for heterogeneous muhi-core graphic processor unit（HMGPU） memory management system is pro-posed in this paper. Fixed-partition is used to manage big-block and continuous data ,and paging management methods is used to manage small-block and non-continuous data.The memory management system is designed and simulated in Verilog, and it is verified to be valid in FPGA. Experimental results show that the system can provide effectively 2 021.2 MB/s memory bandwidth for HMGPU.
出处
《电子技术应用》
北大核心
2013年第5期38-40,43,共4页
Application of Electronic Technique
基金
国家自然科学基金重点项目(61136002)
关键词
异构多核图形处理器
实时并行
硬件实现方法
存储管理系统
heterogeneous multi-core graphic processor
real-time and parallel
hardware method
memory management system
