基于System Verilog的可重用验证平台

The design and implementation of a reusable verification platform based on System Verilog

采用System Verilog语言设计了一种具有层次化结构的可重用验证平台,该平台能够产生各种随机、定向、错误测试向量,并提供功能覆盖率计算。将验证平台在Synopsys公司的VCS仿真工具上运行,并应用到包交换芯片的仿真验证中。仿真结果显示,新设计的验证平台能通过修改随机信号约束条件和产生随机信号的权重值,使芯片的功能覆盖率达到100%。

Design a reusable verification platform with a hierarchical structure employing system verilog language. This verifica-tion platform can generate targeted, random, and error test vectors. The platform also facilitates the computing of functional cover-age. Running this platform on VCS tools of Synopsys Corporation, meanwhile using it to simulate packet switch chip. The result shows that the functional coverage of chip can achieve 100% through revising restraint condition of random signal and weight value using to generate random signal.