基于FPGA的高帧频CCD成像系统设计

System Design of High Frame Rate CCD Image Capture Based on FPGA

为满足机器视觉对于相机的高速、高分辨率要求,设计了一种基于帧转移CCD、FPGA以及千兆网的高帧频成像系统。在系统总体结构的基础上,介绍了图像传感器的外围驱动电路设计、图像传感器驱动控制模块、图像数据高速缓存模块以及千兆网数据传输模块。测试结果显示,系统初步具备了产生1 K×1 K分辨率下94 f/s的驱动时序,同时千兆网传输带宽也初步满足了系统要求。

A high frame rate imaging system based on frame transfer CCD, FPGA and GigE is designed to sat- isfy the high speed and resolution requirement of machine version. At first, the overall structure is given, and then severally introduced the image sensor driving circuits, driver timing controlling mode, image data high speed buffer mode and GigE data transference mode. The test result shows that the system property tentatively meets 94 f/s at 1 K x 1 K resolution.