基于FPGA的全数字相干解调器的实现

An Implementation of All-Digital Coherent Demodulator Based on FPGA

相干解调方案的抗噪能力和误码性能优良,广泛用于全数字接收机中.载波同步和位同步是其中的关键技术,直接影响到解调性能.本文以QPSK信号为例,用修正科斯塔斯环实现载波同步,用基于数字内插和Gardner算法的锁相环结构恢复定时时钟,并从工程应用的角度论述了相干解调器的硬件设计要点.最后在低成本FPGA芯片上验证了设计的可行性和正确性,该解调器抗噪性能良好,高速且实时,具有很大的工程参考价值.

Coherent demodulation has excellent noise immunity and error performance, widely used in the all--digital receiver. Carrier synchronization and bit synchronization are the key technologies directly affecting the demodulation performance. Take QPSK signal for example, this paper uses evolutionary costas loop to achieve carrier synchronization, and PLL structure based on digital interpolation and Gardner algorithm to recover timing clock. From the perspective of project application, some key points of hardware implementation are discussed in detail. The feasibility and correctness of this design are verified on a low--cost Field Programmable Gate Array （FPGA） chip, the demodulator has good anti-- noise, high-- speed and real-- time performance, with great reference value of engineering.