期刊文献+

低功耗CMOS差分环形压控振荡器设计 被引量:10

A Design of Low Power Consumption Differential Voltage-Controlled Ring Oscillator
下载PDF
导出
摘要 提出了一个基于0.18μm标准CMOS工艺实现的四级差分环形压控振荡器.全差分环形压控振荡器采用带对称负载的差分延时单元.仿真结果表明,压控振荡器的频率范围在最坏情况为0.21~1.18GHz;偏离中心频率10MHz情况下,压控振荡器的相位噪声为-118.13dB/Hz;1.8V电源电压下,中心频率为600MHz时,压控振荡器的功耗仅有4.16mW;版图面积约为0.006mm2,可应用于锁相环和频率综合器设计中. A 4--stage differential voltage--controlled ring oscillator base on 0. 18μm standard CMOS technology is proposed in this paper. This full differential voltage--controlled ring oscillator adopted differential delay cell with symmetric load. Simulation results of the oscillator show that the tuning frequency rang from 0. 21 to 1.18GHz at worst case, the phase noise of this oscillator is lower than --118. 13dBc/Hz at 10MHz offset frequency, the power consumption of this oscillator is only 4. 16mW at central frequency is 600MHz with 1.8V power supply, and the layout area of the oscillator is only 0. 006mm2. Therefore, this differential voltage-- controlled ring oscillator is applicable for phase--locked Loop and frequency synthesis.
出处 《微电子学与计算机》 CSCD 北大核心 2013年第5期104-107,共4页 Microelectronics & Computer
基金 教育部支撑项目(625010107)
关键词 低功耗 CMOS差分环形压控振荡器 锁相环 相位噪声 low power consumption CMOS differential ring VCO phase--locked loop phase noise
  • 相关文献

参考文献9

  • 1Floyd M Gardner,著,姚剑清,译.锁相环技术[M](3版).北京:人民邮电出版社,2007.
  • 2John G Maneatis, Mark A Horowitz. precise delay generation using coupled oscillators[J]. IEEE Journal Of Solid-State Circuits, 1993, 28(12):1273-1282.
  • 3桑红石,方海涛,余萌,王文,谢连波.环形振荡器对称负载特性分析[J].微电子学与计算机,2011,28(5):197-200. 被引量:6
  • 4Behzad Razavi. Design of analog CMOS integrated cir- cuits[M]. New York, USA: McGraw-Hill, 2011.
  • 5伍翠萍,何波,于奇,陈达.一种低电压低功耗的环形压控振荡器设计[J].微电子学与计算机,2008,25(5):69-72. 被引量:13
  • 6蔡志民,陈莹梅,李智群,章丽,李伟.GPS射频接收芯片中低功耗压控振荡器的设计[J].微电子学,2009,39(6):790-792. 被引量:3
  • 7SUN Ling,TANG Lu,JING Wei-ping,XIA Jun.CMOS ring VCO for UHF RFID readers[J].The Journal of China Universities of Posts and Telecommunications,2010,17(3):20-23. 被引量:1
  • 8J K Panigrahi, D P Acharya. Performance analysis and design of wideband CMOS voltage controlled ring os- cillator[C]// IEEE 5th International Conference on In- dustrial and Information Systems Proceedings, ICIIS 2010, India:IEEE, 2010: 234-238.
  • 9Luciano Secerino de Paula, Sergio Bampi, Eric Fabris et al. A high swing low power CMOS differential volt- age- controlled ring oscillator[C]//14th IEEE Inter- national Conference on Electronics, Circuits and Sys- tems Proceedings, ICECS 2007. Marrakech: IEEE, 2007, 498-501.

二级参考文献20

  • 1肖杜,李永峰,朱小飞,李卫民.基于数模混合仿真的PLL系统设计[J].微电子学与计算机,2006,23(8):73-75. 被引量:6
  • 2杨丰林,闵昊,沈绪榜.CMOS电感电容压控振荡器中对称噪声滤波技术的研究[J].微电子学与计算机,2007,24(5):41-44. 被引量:5
  • 3BEST R E. Phase-locked loops [M]. 5th Ed. New York: McGraw-Hill, 2003.
  • 4RAZAVI B. Design of analog CMOS integrated circuits[M]. New York: McGraw-Hill, 2000.
  • 5RAZAVI B. A study of phase noise in CMOS oscillators [J]. IEEEJ Sol Sta Circ, 1996, 31(3): 331-343.
  • 6WANG X-Y, ZHU E, XIONG M-Z, et al. Design of 11 GHz CMOS ring VCO [J]. Chinese J Semicond, 2005, 26(1): 187-191.
  • 7HERZEL F, RAZAVI B. A study of oscillator jitter due to supply and substrate noise [J]. IEEE Circ and Syst Ⅱ, 1999, 46(1): 56-62.
  • 8ALIOTO M, PALUMBO G. Design strategies for source coupled logic gates [J]. IEEE J Trans Circ and Syst, 2003, 50(5): 640-654.
  • 9Maneatis J G. Low--jitter process--independent DLL and PLL based on self-biased techniques[J]. 1EEE Journal of Solid-State Circuits, 1996,31(11) : 1723-1732.
  • 10Maneatis J G. Self--biased high--bandwidth low--jitter 1 --to--4096 multiplier clock generator PLL[J]. IEEE Journal of Solid-State Circuits, 2003,38(11) : 1795-1803.

共引文献18

同被引文献48

  • 1冯平,吴贵臣.智能调制解调器与单片机系统的接口及控制[J].微计算机应用,2005,26(2):211-213. 被引量:1
  • 2曾健平,章兢,谢海情,刘利辉,曾云.1.8GHz宽带低相位噪声CMOS压控振荡器设计[J].湖南大学学报(自然科学版),2007,34(6):37-40. 被引量:4
  • 3陈剑,杨银堂.CMOS图像传感器研究[J].电子科技,2007,20(9):17-21. 被引量:9
  • 4CHATTOPADHYAY S. Tutorial T3: low power design techniques for nanometer design processes - 65 nm and smaller [ C ] // Proceedings of the 20'h International Conference on VLSI Design Held Jointly with 6'h Interna- tional Conference on Embedded Systems. Bangalore, In- dia, 2007: 5.
  • 5PARDO M, AYAZI F. A band reject nested PLL clock cleaner using a tunable MEMS oscillator [ J ]. IEEE Transactions on Circuits and Systems: I, 2014, 61 (3): 653-662.
  • 6WU T, HANUMOLU P K, MAYARAM K, et al. Me- thod for a constant loop bandwidth in LC-VCO PLL frequency synthesizers [ J]. IEEE Journal of Solid-State Circuits, 2009, 44 (2): 427-435.
  • 7YU X Y,SUN Y F, RHEE W, et al. An FIR-embedded noise filtering method for Deha-Sigma fractional-N PLL clock generators [ J]. IEEE Journal of Solid-State Cir- cuits, 2009, 44 (9): 2426-2436.
  • 8SAI A, KOBAYASHI Y, SAIGUSA S, et al. A digitally stabilized type-III PLL using ring VCO with 1.01 psrms inte- grated jitter in 65 nm CMOS [ C ] //Proceedings of IEEE International Solid-State Circuits Conference Digest of Tech- nical Papers. San Francisco, CA, USA, 2012: 245-250.
  • 9LEE S Y, ITO H, ISHIHARA N, et al. A novel direct injection-locked QPSK modulator based on ring VCO in 180 nm CMOS [ J]. IEEE Microwave and Wireless Com- ponents Letters, 2014, 24 (4): 269-271.
  • 10HAJIMIRI A, LIMOTYRAKIS S, LEE T H. Jitter and phase noise in ring oscillators [ J ]. IEEE Journal of Solid-State Circuits, 1999, 34 (6): 790-804.

引证文献10

二级引证文献28

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部