一种12位100MSPS采样保持电路的设计

Design of a 12-bit 1000MSPS CMOS Sample and Hold Circuit

基于0.13μm/3.3V CMOS工艺,设计了一种用于12bit 100MSPS Pipeline ADC的采样保持(S/H)电路.采用具有高线性度双边对称的无馈通自举采样开关,获得高增益、宽带宽的跨导前馈补偿共源共栅两级全差分跨导放大器,以及能显著降低增益误差的相关双采样S/H拓扑结构来搭建S/H电路.仿真结果表明:当在11.27MHz的输入信号,111MHz的采样信号下,该S/H电路无杂散动态范围(SFDR)86.4dB,功耗为32mW.

A 12bit 100 MSPS pipelined analog--to digital converter （ADC） sample and hold circuit is designed based 0. 13μm/3. 3V CMOS process. In this circuit , a high linearity Double Side Symmetrical No Feed Through （DSSNFT） bootstrapped switch , a high gain wide bandwidth Cascode Transconductance Feed Forward （CTFF） compensation two-stage fully differential OTA and a low gain--error correlated double sampling S/H topology structure are used to build S/H circuit. The simulation results show that SFDR can reach 86. 4dB with input signal 11.27MHz and sample signal 111MHz. Power consumption is about 32mW at a 3.3V supply.