基于VHDL的数字系统层次化设计方法

Hierarchy design method of digital system based on VHDL

通过对数字频率计系统的设计,介绍了基于VHDL语言的数字系统层次化设计方法。首先将数字系统按功能划分为不同的模块,各模块电路的设计通过VHDL语言编程实现,然后建立顶层电路原理图。使用MAX+PLUSII开发软件完成设计输入、编译、逻辑综合和功能仿真,最后在CPLD上实现数字系统的设计。结果表明,使用这种设计方法可以大大地简化硬件电路的结构,具有可靠性高、灵活性强等特点。

The hierarchy design method of digital system based on VHDL is proposed through the design of digital frequency meter system in this paper. Firstly, it divides the frequency meter into different function module and writes VHDL code to describe each module circuit. Then, it creates the schematic diagram of top circuit. Design input, compiled, logic synthesize and function simulation are accomplished by using MAX＋PLUS II. In the end, digital frequency meter is implemented in CPLD. The results show that the design method can greatly simplify the complexity of hardware circuit structure. Its characteristic is high reliability and strong flexibility.