一种5倍频电路的设计

Design of a Fivefold Frequency Multiplier

介绍了一种实用化、低相位噪声的5倍频电路,采用一种新颖的电路结构进行设计,用SMT工艺加工制作。对各单元电路进行了原理分析,通过ADS软件进行仿真,最后对成品电路进行测试,测试结果与仿真结果相同。与其他5倍频电路相比,该电路具有相位噪声低、杂散低、结构简单、一致性好等优点,可广泛用于通信、雷达、频率合成器、测量等领域。

A practical fivefold frequency multiplier circuit was presented, which was designed with a novel topology and fabricated with SMT. Operational principle for each circuit cell was analyzed and simulated with ADS, Simulation results were validated by test results. Featuring lower phase noise, lower spur, simpler topology and better consistency, compared with other fivefold frequency multipliers, the circuit is applicable for communication, radar, frequency synthesizer, and instrumentation.