dV_(ss)/dt触发N阱CMOS器件闩锁失效的研究

Study on dV_(ss)/dt Triggered Latch-Up Effect of N-Well CMOS Device

从半导体器件物理的角度分析了dVss/dt触发N阱CMOS器件的闩锁失效现象。当瞬时负电压脉冲峰值满足Vss_peak<Vss0(导通临界值约为-0.8V)时,CMOS器件发生闩锁效应。dVss/dt外界触发作用消失后,为了达到稳定闩锁效应状态,存储在寄生PNPN结构中耗尽电容的电荷量Qc要大于Qc0(临界值),需要足够的脉冲宽度和较小的晶体管渡越时间。Silvaco瞬态仿真验证表明,该研究结果可用于改善CMOS集成电路的可靠性设计。

Latch-up failure of N-well CMOS device triggered by dVss/dt was analyzed in terms of physics of semiconductor devices.It was observed that latch-up effect was caused by transient negative voltage pulse on Vss contact,when the pulse peak Vss_peak was smaller than Vss0（about-0.8 V）.After transient pulse roll-off,charge Qc stored in parasitic SCR（PNPN） junction depleted capacitor must be greater than threshold value Qc0 to maintain latch-up stability.The charge Qc was dependent on transient pulse width and transit time of parasitic bipolar transistors.Silvaco transient simulation was made to verify the work,which was useful for improving reliability design of CMOS IC＇s.