坩埚表面改性对冶金法多晶硅电学性能的影响

Effect of crucible surface modification on the electrical properties of multicrystalline silicon using metallurgical route

冶金法制备太阳能级多晶硅所用石墨坩埚含有不同类型的金属杂质,这些杂质通常会降低硅锭的电阻率和少子寿命等电学性能。本文研究了坩埚表面改性对冶金法多晶硅电阻率和少子寿命的影响。通过在不同冷凝速率条件下,对工业硅原料在改性前后的坩埚内提纯。经对铸锭切片的电阻率测试得出:坩埚表面改性使冶金法多晶硅锭的电阻率得到了明显的提高,电阻率的最高值由原来冷凝速率为20μm/s时的110mΩ.cm提高到30μm/s时227mΩ.cm;经对铸锭切片的少子寿命测试得出:冶金法多晶硅的少子寿命在冷凝速率20μm/s时最高,坩埚表面改性使少子寿命由原来的0.81μs提高到1.91μs。

Many different types of metal impurities in the graphite crucibles would reduce the electrical properties of multicrystalline silicon,such as resistivity and minority carrier lifetime,during the purification of metallurgical grade silicon.In this paper,the influence of the crucible surface modification on the resistivity and minority carrier lifetime of multicrystalline silicon was investigated.The electrical properties were tested under different condensation rates in modified and non-modified crucibles,respectively.The results showed that the resistivity and minority carrier lifetime in the modified crucible were both significantly improved,the highest resistivity values from 110mΩ·cm to 227mΩ·cm under condensation rate of 20μm/s to 110 to 30μm/s,and the minority carrier lifetime increased from 0.81μs to 1.91μs,the highest value was obtained at the condensation rate of 20μm/s.