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高速数字I/O缓冲器瞬态行为建模及其在同步开关噪声分析中的应用 被引量：2

Transient Behavioral Modeling of the High speed Digital I/O Buffer and Its Application in the Analysis of Simultaneous Switching Noise
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摘要 本文阐述了从最新版本的IBIS(I/OBufferInformationSpecification)建模数据中构造高速数字I/O缓冲器的瞬态行为模型的推导过程 ,获得了建模所需要的充分条件 .与相应的晶体管级模型 (SPICE模型 )相比 ,该方法在获得了更高仿真精度的同时 ,提高了具有大量同步开关器件芯片互连的仿真速度 .采用这些模型有效地分析了多芯片互连非线性电路中的同步开关噪声 。 The derivation procedure in building transient behavioral models of high speed digital I/O buffers from latest version IBIS modeling data is given,and the sufficient condition for modeling is obtained.Compared with the corresponding transistor level models (SPICE models),this IBIS model speeds up the chip simulations including interconnect and a large number of simultaneous switching devices with better accuracy.Finally,the SSN(Simultaneous Switching Noise) in multi chip interconnect nonlinear circuits is analyzed efficiently with this model,verifying the advantage of signal transmission with difference waveforms.
作者 蔡兴建 毛军发 陈建华 李征帆
机构地区 上海交通大学电子工程系
出处 《电子学报》 EI CAS CSCD 北大核心 2000年第11期36-38,42,共4页 Acta Electronica Sinica
基金 国家自然科学基金! (No .697760 2 2 ) 上海交大大众电脑集团葛守仁教授奖教金
关键词 高速数字I/O缓冲器 瞬态行为模型 同步开关噪声 IBIS model high speed digital I/O buffer transient behavioral model SSN
分类号 TP334.4 [自动化与计算机技术—计算机系统结构]
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参考文献6

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  • 4[4]W.Hobbs,A.Muranyi,R.Rosenbaum and D.Telian.IBIS:I/O Buffer Information Specification [EB/OL].Overview http://www.vhdl.org,Intel Corporation,1994.
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同被引文献15

  • 1霍津哲,蒋见花,周玉梅.一种基于0.18μm的同步开关输出噪声模型和仿真方法[J].电子器件,2005,28(4):842-845. 被引量：2
  • 2Bogatin E. Signal integrity-simplified[M]. Prentice Hall PTR, 2003.
  • 3Shahparnia S,Ramahi O M. Simultaneous switching noise mitigation in PCB using [J]. Cascaded Highimpedance Surfaces, Electronics Letters, 2004, 40 (2): 123-126.
  • 4Chen G, Melde K, Prince J. The applications of EBG structures in power/ground plane pair SSN suppression[J]. IEEE Microwave and Wireless Components Letters, 2004, 15 (3) : 101-103.
  • 5Varma A, Glaser A, Lipa S, Steer M, Franzon P. The development of a macro-modeling tool to develop IBIS models [A]. Proc.12th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP) [C]. 2003. 277-280.
  • 6Wang ying, Han ngee tan. The development of analog SPICE behavior model based on IBIS model [A]. Proceedings of Ninth Grate Lakes symposium on VLSI [C]. 1999. 101-104.
  • 7Stievano I S, Maio I A, Cannero F G. Parametric macromodles of digital I/O ports [J]. IEEE Trans. Advanced Packaging, 2002, 25: 255-264.
  • 8Stievano I S, Maio I A, Cannero F G. Behavioral models of I/O ports from measured transient waveforms [J]. IEEE Trans. Instrum. Meas., 2006, 51: 1266-1270.
  • 9I S Stievano, I A Maio, F G Cannero. Macromodeling via parametric identification of logic gates [J]. IEEE Trans. Advanced Packaging, 2004, 27(1): 15-23.
  • 10B Mutnury, M Swaminthan, J P Libous. Macromodeling of nonlinear digital I/O drivers [J]. IEEE Trans. Advanced Packaging, 2006, 29: 102-113.

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电子学报
2000年 第11期

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