VLSI互连寄生电容准三维多极加速提取

A Virtual 3 D Multipole Accelerated Extractor for VLSI Parasitic Interconnect Capacitance

随着VLSI向深亚微米发展 ,需要快速而精确地计算互连寄生电容以保证高性能电路设计的正确性 .本文介绍一个单介质准三维电容提取软件 .在位势理论建立的间接边界积分方程中 ,它在导体表面采用线电荷近似面电荷的思想简化 3 D结构 ,并采用多极加速法进一步降低计算复杂度 .由于既保留了三维形体的空间架构 ,又使大量电荷积分降为一维 ,取得了精度与速度的良好平衡 .数值计算结果表明 ,其计算复杂性为O(n) 。

With development of the VLSI circuits towards the deep submicron,it is in great need of calculating the parasitic capacitance quickly and precisely to gain correct design of circuits with high performance.A virtual 3 D extractor of the single dielectric is presented in this paper.In the indirect boundary integral equations based on the potential theory,the plane charge distribution on the surface of conductors is replaced with mesh charge distribution to reduce the complexity of 3 D structure,and we use the multipole accelerated algorithm to further depress the computational complexity.Since it reserves the geometry of three dimensional structure and reduces the integral of electrical charge from two dimensions to one dimension,it obtains not only enough accuracy but also a high computational speed.Numerical results show that its computational complexity is about O(n) ,where n is the number of the discrete variables.