一种基于FPGA控制的新型CCD驱动电路设计

A new design method of CCD driving circuit based on FPGA control model

设计出一种新型的FPGA编程控制CCD驱动电路方法。通过仿真与实验结果表明,该方法能实现CCD的驱动时序、采样和信号输出。该方法采用VHDL语言,电路设计简单化、直观化、稳定性高,容易修改;采用PCI总线,电路能迅速完成采集和传输。该设计具有较好的性价比和抗噪声性能。

A field-p cult design method rogrammable gate was presented. array （FPGA） -based charge-coupled device （CCD） By using very high speed hardware description drive cir- language （VHDL）, the design method enables the design to be simple, visualized, stable and easy to modi- fy. With peripheral component interconnecting （PCI） bus, the circuit can rapidly gather and trans- mitt data signals. The simulation results show that the method can achieve CCD time sequence driv- ing, sampling and signal output with lower cost and decreased noise.