FPGA设计中的同步设计

The Synchronous Design of the FPGA Design

在FPGA设计中,时序设计是一个系统性能的主要标志,同步设计是实现设计目的关键。建立模型,进行功能性分析是前奏;建立起来的模型要想正确在FPGA内布线,所有的逻辑关系必须是同步运行。时钟同步要求所有事件的发生都是以同一时钟的边沿作为标准,所有进入FPGA内部的信号要尽可能用相应的时钟网络来同步。

The synchronous design is the sign of the system performance in FPGA design. ItJs the key to implement the design. First, the model is constituted and the functions are analyzed. All of the logic cells must be synchronous, which is the key of the design. The synchronous clock requires that all of the ceils change at the same clock edge. All of the signals in the FPGA must be synchronous with the same clock.