应用于三维集成电路解析式布局的层分配算法

Chip layer assignment method for analytical placement of 3D ICs

层分配是解析式三维集成电路布局算法中的关键一步。解析式布局需要通过层分配将连续的三维空间中的单元划分到二维的芯片层上,这个过程会破坏之前三维空间中得到的连续解。为了实现从优化的三维布局到合法的多层二维结构的平滑过渡,提出一种使用最小代价流的层分配方法,尽可能地继承三维优化结果,保护解空间。将此层分配算法嵌入到多层次的解析式三维集成电路布局算法中,以总线长和穿透硅通孔数目的加权总和为目标,面积密度为约束条件,对比当前其他三维布局算法,该算法得到较好的线长结果、穿透硅通孔数量和运行时间。

Chip layer assignment is a key step in analytical placement of 3D Integrated Circuits （ICs）. Analytical placement could face the conversion from 3D continuous space in z-direction to several connected 2D chip layer spaces by layer assignment. However, layer assignment may destroy the previous optimal solution in 3D continuous space. To realize the transition from an optimal 3D placement to a legalized, layer-assigned placement smoothly, a layer assignment method was proposed by using the minimum cost flow, which protected solution space and inherited optimal wirelength at most. The layer assignment method was embedded in a multilevel non-linear placement of 3D ICs which minimized the weighted sum of total wirelength and Through Silicon Via （TSV） number subject to area density constraints. The proposed placement algorithm can achieve better wirelength results, TSV number and run time in comparison with the recent 3I） placement methods.