HEVC整数DCT变换与量化的FPGA实现

FPGA Implementation of Integer DCT Transform and Quantization for H.265/HEVC

HEVC编码框架采用了比H.264/AVC面积更大的DCT变换和更为灵活的自适应量化,在提高数据处理速度的同时,降低了编解码的失真率。基于HEVC的变换量化原理和模块化的思想,采用并行流水线结构和无乘法器方案实现了整数DCT变换及量化部分。系统采用MODELSIM进行功能仿真,基于Altera公司的Cyclone II系列可编程逻辑器件进行硬件验证测试,其最大时钟频率在170 MHz以上,数据处理能力在2 824 Mpixel/s以上,满足HEVC编码标准的性能要求,为HEVC编解码标准的硬件实现提供了参考。

HEVC coding frame adopts larger size of DCT and more flexible adaptive quantization than H.264/AVC,enhancing the speed of data processing and reducing the distortion of encoding and decoding. According to the principle of the transform and quantization of HEVC and the idea of modularization, the implementation the DCT and quantization part with pipelining structure and non-multiplier resolution. The system is simulated in MODELSIM and verified in the Cyclone II-based FPGA. Its maximal work frequency is more than 170 MHz,the maximal throughput is more than 2 824 Mpixels/s,satisfying the performance requirement of HEVC and providing a reference for HEVC hardware implementation.