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具有MUX模式的新型LUT结构及其优化算法

A new LUT construct with MUX mode and the corresponding optimization algorithm
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摘要 针对传统4-LUT实现多路选择器(multiplexer,MUX)时逻辑利用率低,延迟略大的不足,提出具有MUX模式的新型查找表(look-up table,LUT)结构—M-LUT.M-LUT通过改进传统4-LUT结构,使其在兼容传统4-LUT功能的基础上新增MUX模式,仅需配置1个MUX模式的M-LUT即可实现1个MUX4功能,且延迟仅为一级LUT延迟.为M-LUT设计配套的优化算法,以提高M-LUT利用率.实验结果显示,采用M-LUT加优化算法后,LUT资源占用平均减少8.4%,电路时钟频率平均提高3.1%. A novel LUT （look-up table） construction method with MUX mode called M-LUT is proposed to solve the inefficient use of area, and the delay problem of multiplexer （MUX） implementation with the traditional 4-LUT. M-LUT is derived by modifying the traditional 4-LUT. This M-LUT not only retains all functions of the 4-LUT but also develops an extra MUX mode. Only one configuration of M-LUT under MUX mode was needed to implement a MUX4, and the delay was reduced to LUT level one. A corresponding optimization algorithm is also designed for M-LUT to reconstruct MUX tree into MUX4 cells. Experimental results show that with the M-LUT and the optimization algorithm. The LUT resource utilization is reduced by 8.4% , and the clock frequency is increased by 3.1% on average.
作者 郭旭峰 王作建 李明 于芳
机构地区 中国科学院微电子研究所 中国科学院大学物理学院 飘石科技有限公司
出处 《深圳大学学报（理工版）》 EI CAS 北大核心 2013年第3期248-253,共6页 Journal of Shenzhen University(Science and Engineering)
基金 国家科技重大专项经费资助项目(Y1GZ212002)~~
关键词 微电子学 多路选择器 查找表 MUX优化算法 现场可编程门阵列 电子设计自动化 microelectronics multiplexer look-up table MUX optimization algorithm field programmable gatearray electronic design automation
分类号 TP332.102 [自动化与计算机技术—计算机系统结构]
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参考文献10

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深圳大学学报（理工版）
2013年 第3期

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