摘要
为满足工程需要,设计并实现了一种基于锁相环芯片ADF4360-8的低噪声高稳定度频率合成器。给出了该频率合成器的设计原理、硬件组成、软件设计及其实现方法与流程。重点介绍了一些主要芯片和关键电路。该锁相环频率合成器输出的100 MHz较高频周期信号的峰-峰值达到2.16V,能直接驱动TTL电路。测试结果表明该频率合成器输出的频率信号稳定,噪声低,幅度大。
For satisfying the engineering needs, a phase locked loop frequency synthesizer with high stability and low phase noise is designed and implemented based on the phase locked loop chip ADF4360-8.The design principle, hardware constitution, software design and the implementation are described. Some main chips and the key circuits are introduced with emphasis. The amplitude of 100 MHz output signal for the frequency synthesizer reaches 2.16 V(peak-peak), being able to directively drive the TTL circuit. The test results show that the output signals of the frequency synthesizer are characterized by good stability, low noise and high amplitude.
出处
《时间频率学报》
CSCD
2013年第2期75-83,共9页
Journal of Time and Frequency
基金
国家自然科学基金资助项目(10773012)